Starting from the 45 nm CMOS integrated circuit technology, with continuous reduction in the device feature size, the equivalent oxide thickness (EOT) of a gate insulating dielectric layer in a CMOS device must be reduced synchronously to suppress the short channel effect. However, the ultra-thin (e.g., 10 nm) conventional oxide layer or oxynitride layer may result in severe gate current leakage since the (relative) dielectric constant is not high (e.g., about 3.9) and the insulating capability can hardly endure the relatively high field strength in such an ultra-small device. Hence, a conventional polysilicon/SiON system is no longer applicable.
In view of this, high-K (HK) dielectric materials are started to be used to manufacture a gate insulating dielectric layer in the industry. However, the interfacial charges and polarization charges of high-K materials will cause difficulty in regulating the threshold of a device, and the combination of polysilicon and high-K materials will produce a Fermi-level pinning effect, thus such combination of polysilicon and high-K materials can not be used for regulating the threshold of a MOSFET, accordingly, the gate electrode shall employ different metal materials to regulate the threshold of a device, that is, using a metal gate (MG)/HK structure.
Metal electrodes of different work functions are needed for regulating the threshold of different MOSFETs, e.g., an NMOS and a PMOS. The regulation method using a single metal gate material may be adopted, but the range of regulation is limited. In an example of a planar SOI multi-gate device with lower standby power employing a single metal gate material, to correspond to a work function of 4.1 eV of n+ polysilicon and a work function of 5.2 eV of p+ polysilicon, an appropriate metal electrode may be selected such that the work function of the gate can be in the vicinity of the median value of the two, e.g., to be 4.65 eV or 4.65±0.3 eV. However, the device threshold is hard to be effectively controlled by such a fine regulation within a small range. The optimal process is to adopt gate electrodes of different metal materials, for example, conduction-band metal is used for the NMOS and valence-band metal is used for the PMOS such that the gate work functions of the NMOS and the PMOS can be located at the edges of the conduction band and the valence band, respectively, e.g., 4.1±0.1 eV and 5.2±0.1 eV, respectively. A detailed study of selection of the materials for these gate metal (including metal nitride) has been made in the industry, and no more unnecessary details will be provided here.
Generally, the existing CMOS dual-metal gate integration process comprises: performing etching to remove the dummy gate from the PMOS and NMOS basic structures to thereby form a PMOS gate trench and a NMOS gate trench, and depositing a gate insulating layer of high-K materials in the two gate trenches; sequentially depositing a first blocking layer such as TiN (and/or an etch stop layer, such as Ta and TaN), a PMOS work function regulating layer (such as TiN), and a second blocking layer (such as TaN) on the gate insulating layer in the PMOS gate trench and the NMOS gate trench; performing selective dry etching to remove the PMOS work function regulating layer and the second blocking layer from the NMOS region, exposing and stopping at the first blocking layer; depositing a NMOS work function regulating layer (such as TiAl and Al) on the second blocking layer of the PMOS region and the first blocking layer exposed at the NMOS region; sequentially depositing a third blocking layer (such as TiN and Ti) and a resistance regulating layer on the entire device, i.e., the NMOS work function regulating layer; performing chemical mechanical polishing (CMP) planariztion to expose an interlayer dielectric (ILD) layer; and performing etching to the ILD to form source and drain contact holes and filling metal to form source and drain contact plugs.
The above existing technology facilitates the Al ions contained in the NMOS work function regulating layer to diffuse quickly, so that they may effectively diffuse to the vicinity of the interface between the gate insulating layer and the first blocking layer, to thereby control the NMOS work function effectively. However, in order to avoid the effect of the Al ions in the NMOS work function regulating layer on the PMOS work function regulating layer, a second blocking layer must be formed and retained in the PMOS region. Thus, in the device structure of the PMOS region, the metal gate structure is extremely complex (comprising three blocking layers), in a condition where the feature size-the gate length is continuously reduced, particularly when the gate length is below 22 nm, since the structure of the multi-layer blocking layer causes a decrease in the space of the resistance regulating layer of the PMOS region which can be filled, problems will occur where the gate resistance is difficult to be effectively reduced due to small size of the resistance regulating layer and the resistivity is increased due to holes formed by insufficient filling.